Verilog-A model of the impurity freeze-out in LDD regions at cryogenic temperatures-Reference-Cited by-同舟云学术

Verilog-A model of the impurity freeze-out in LDD regions at cryogenic temperatures

Published:2023-06-14 Issue:2 Volume:16 Page:93-100
ISSN:2219-0767
Container-title:Modeling of systems and processes
language:en
Short-container-title:

Author:

Osykin Andrey¹,Potupchik Aleksandr²,Panyshev Kirill²

Affiliation:

1. JSC MERI

2. AO "Nauchno-issledovatel'skiy institut molekulyarnoy elektroniki"

Abstract

The article shows the practical implementation of the impurity freeze-out effect in the lightly-doped areas of the drain and source (LDD) in the Verilog-A model of the resistor. This model is based on a theoretical understanding of the freeze-out effect at cryogenic temperatures and data from the TCAD simulation of a MOSFET. The TCAD simulation data were represented by transconductance characteristics of n- and p-channel transistors Id(Vg) in linear mode (Vd=0.1 V) at temperature range from -200 °C to 27 °C for transistors with dimensions 10 um × 10 um. The model is applicable to the use as part of a macromodel of a MOSFET transistor for a CMOS bulk process with a supply voltage of 1.8 V and a minimum channel length of 0.18 um. Since the model is based on a limited set of TCAD modeling data, this version is the basis on which it is possible to build a geometrically scalable model that will be valid over the entire range of drain voltages.

Publisher

Infra-M Academic Publishing House

Subject

General Medicine

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