Border Trap Extraction with Capacitance- Equivalent Thickness to Reflect the Quantum Mechanical Effect on Atomic Layer Deposition High-k/In0.53Ga0.47As on 300-mm Si Substrate-Reference-Cited by-同舟云学术

Border Trap Extraction with Capacitance- Equivalent Thickness to Reflect the Quantum Mechanical Effect on Atomic Layer Deposition High-k/In0.53Ga0.47As on 300-mm Si Substrate

Published:2019-07-08 Issue:1 Volume:9 Page:
ISSN:2045-2322
Container-title:Scientific Reports
language:en
Short-container-title:Sci Rep

Author:

Rahman Md. Mamunur^ORCID,Kim Jun-Gyu,Kim Dae-Hyun,Kim Tae-Woo^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Multidisciplinary

Link

http://www.nature.com/articles/s41598-019-46317-2.pdf

Reference44 articles.

1. Del Alamo, J. A. Nanometre-scale electronics with III–V compound semiconductors. Nature 479, 317–323 (2011).

2. Lin, H. C., Wang, W. E., Brammertz, G., Meuris, M. & Heyns, M. Electrical study of sulfur passivated In0.53Ga0.47As MOS capacitor and transistor with ALD Al2O3 as gate insulator. Microelectronic Engineering, https://doi.org/10.1016/j.mee.2009.03.112 (2009).

3. Lin, D. et al. Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution. In IEEE International Electron Devices Meeting (IEDM) 1–4, https://doi.org/10.1109/IEDM.2009.5424359 (IEEE, 2009).

4. Taoka, N. et al. Impact of Fermi Level Pinning inside Conduction Band on Electron Mobility of InxGa1−xAs MOSFETs and Mobility Enhancement by Pinning Modulation. In International Electron Devices Meeting 27.2.1–27.2.4, https://doi.org/10.1109/IEDM.2011.6131622 (IEEE, 2011).

5. Heyns, M. et al. Advancing CMOS beyond the Si roadmap with Ge and III/V devices. In International Electron Devices Meeting 3, 13.1.1–13.1.4 (IEEE, 2011).

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