Funder
DARPA 3DSoC Program, Stanford SystemX Alliance
NSF/NRI/GRC E2CDA Program, DARPA 3DSoC Program, Stanford SystemX Alliance
DARPA 3DSoC Program
CEA-LETI
Stanford SystemX Alliance
NSF/NRI/GRC E2CDA Program, DARPA 3DSoC Program, Stanford SystemX Alliance, Intel Corporation
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Instrumentation,Electronic, Optical and Magnetic Materials
Reference54 articles.
1. Aly, M. M. S. et al. Energy-efficient abundant-data computing: the N3XT 1,000. Computer 48, 24–33 (2015).
2. Aly, M. M. S. et al. The N3XT approach to energy-efficient abundant-data computing. Proc. IEEE 107, 19–48 (2019).
3. Donato, M. et al. On-chip deep neural network storage with multi-level eNVM. In Proc. 55th Design Automation Conference (DAC) https://doi.org/10.1145/3195970.3196083 (IEEE, 2018).
4. Li, H., Bhargava, M., Whatmough, P. N. & Wong, H.-S. P. On-chip memory technology design space explorations for mobile deep neural network accelerators. In Proc. 56th Design Automation Conference (DAC) https://doi.org/10.1145/3316781.3317874 (IEEE, 2019).
5. Hestness, J. et al. Deep learning scaling is predictable, empirically. Preprint at https://arxiv.org/abs/1712.00409 (2017).
Cited by
17 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Aries: A DNN Inference Scheduling Framework for Multi-core Accelerators;Proceedings of the 2024 5th International Conference on Computing, Networks and Internet of Things;2024-05-24
2. NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching;ACM Transactions on Design Automation of Electronic Systems;2023-12-18
3. MC-ELMM: Multi-Chip Endurance-Limited Memory Management;Proceedings of the International Symposium on Memory Systems;2023-10-02
4. Exploration of Time Reversal for Wireless Communications within Computing Packages;Proceedings of the 10th ACM International Conference on Nanoscale Computing and Communication;2023-09-20
5. Instruction-Level Modeling and Evaluation of a Cache-Less Grid of Processing Cells;2023 Forum on Specification & Design Languages (FDL);2023-09-13