Design and Implementation of High-Performance FPGA Accelerator for Non-Separable Discrete Fourier Transform Optimizing Real-Time Image and Video Processing

Abstract

In image processing applications, the Non-separable Discrete Fourier Transform (NDFT) plays a crucial role in analyzing complex patterns and structures. This paper presents the design and implementation of a highperformance FPGA accelerator tailored for efficiently computing the NDFT in image processing tasks. The proposed design leverages parallel processing, memory optimization, and pipelining techniques to achieve significant improvements in throughput while maintaining low latency. The effectiveness of the FPGA accelerator is demonstrated through extensive performance analysis and comparisons with existing methods. The NDFT is essential for analyzing multidimensional data such as images, where the traditional Fast Fourier Transform (FFT) may not be applicable due to non-separable structures. However, implementing NDFT efficiently on conventional computing platforms poses significant challenges, particularly in terms of computational complexity and memory access patterns. FPGA-based accelerators offer a promising solution by exploiting the inherent parallelism and reconfigurability of FPGA architectures. The proposed FPGA accelerator for NDFT computation is designed using a combination of parallel processing, memory optimization, and pipelining techniques. Industrial robots, medical imaging, and surveillance systems were only a few of the many applications that our proposed study exhaustively tested to determine how well our method worked. The software libraries needed to take advantage of the SoC’s hardware acceleration features were synthesized using Vivado® High-Level Synthesis (HLS). Our findings show that processing speed and resource usage are significantly improved, and throughput and latency reduction are significantly improved as well. The method’s versatility and scalability are further demonstrated by its remarkable adaptation to a wide range of image and video processing jobs. The proposed work provides empirical evidence of our approach’s efficacy by quantifying the performance improvements realized through quantitative analysis. Finally, our research shows that Xilinx Zynq®-7000 SoC devices can be revolutionized with hardware acceleration and enhanced feature identification integrated. Our method allows real-time video and image processing applications to scale more efficiently by overcoming the difficulties of complicated computing jobs. This paradigm changes signals the beginning of a new age of invention and advancement, and it will have far-reaching consequences for sectors that depend on autonomous systems, cryptography, and computer-human interaction.