An Efficient Design of a Three-Layer Magnitude Comparator for Nano-Scale IoT Applications Based on QCA Technology

Abstract

The difficulty of further downscaling CMOS technology arises from the restriction of feature size reduction. Quantum-dot cellular automata (QCA) emerges as a paradigm-shifting successor to CMOS, heralding a new era of effective digital design at the nanoscale. It stands as an enticing frontier in nanoscale computing, with limited exploration into the realms of smaller QCA cells, elevated processing speeds, and more compact area requirements across diverse circuits. Within the intricate landscape of decoding circuits and process controllers, the binary comparator assumes a role of paramount significance. On the other hand, the quickly developing Internet of Things (IoT) market aims to produce high-speed, low-power gadgets. A comparator is a crucial component in the analog-to-digital conversion process used by IoT devices. In order to meet the power and latency requirements of IoT devices, a high-speed, low-power comparator is greatly required. Consequently, the strategic design of comparators within the QCA framework has ascended to a position of heightened importance in cutting-edge research. This study undertakes the formidable task of conceiving QCA-centric designs for MV32, the majority gate, and the inverter gate, thereby contributing to the development of a sophisticated multi-layered comparator architecture for IoT devices. In the realization of a three-layer comparator implemented in QCA, we attain an impressive feat—a minimal clock zone demanding only a singular clock pulse coupled with exceptional compaction (measuring at a mere 0.03 μm2). Experimental revelations corroborate the substantial advancement of the proposed design over traditional methodologies, particularly in terms of circuit area, cell count, and clock efficiency.