TCFTL: Improved Real-Time Flash Memory Two Cache Flash Translation Layer Algorithm

Author:

He Qinlu1,Bian Genqing1,Zhang Weiqi1,Wu Fenglang2,Li Zhen3

Affiliation:

1. School of Information and Control Engineering, Xi’an University of Architecture and Technology, Xi’an 710054, China

2. The First Affiliated Hospital of Xi’an Jiaotong University, Xi’an 710048, China

3. Shaan Xi Institute of Metrology Science, Xi’an 710043, China

Abstract

The traditional flash translation layer (FTL) algorithm is mainly aimed at optimizing the average response time of flash reading and writing. Since it cannot be updated in place, for the traditional FTL algorithm, it is necessary to find a free page for writing each time. When a block is full, it will redistribute a free block. Therefore, when the flash memory is almost full, a written request will lead to a garbage collection, which will have many write copies, which will lead to a substantial decline in response time. This paper proposes an algorithm that makes full use of spatial locality and temporal locality to optimize the address cache in Demand-based Flash Translation Layer (DFTL) algorithm. In the experiment, this algorithm experiment and good results are obtained.

Publisher

American Scientific Publishers

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

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