Laser–Assisted Mos/Sos Transistor Fabrication

Abstract

ABSTRACTCW laser annealing techniques were incorporated into standard MOS/SOS transistor fabrication procedures and found to be advantageous as compared to conventional furnace methods for electrical activation of ion–implanted source/drain dopants for both N- and P–MOS transistors. Static electrical characteristics of 2.4 μm channel–length transistors are similar for both types of annealing, whereas the speed of devices with cw laser annealed source–drain regions is increased 10 to 40%, depending on the operating voltage.