Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps

Author:

Oppermann Hermann,Hutter Matthias,Klein Matthias,Engelmann Gunter,Toepper Michael,Wolf Jürgen

Abstract

AbstractAu/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail.

Publisher

Springer Science and Business Media LLC

Subject

General Engineering

Reference14 articles.

1. 3 Kallmayer Ch. , Oppermann H. , Kloeser J. , Zakel E. , Reichl H. , Experimental Results on the Self-Alignment Process Using Au/Sn Metallurgy and on the Growth of the σ-CPhase During the Reflow. Proc. International Flip Chip, Ball Grid Array, TAB and Advanced Packaging Symposium, ITAP'95, San Jose, 1995.

2. Spectroscopic measurement of mounting-induced strain in optoelectronic devices

3. 2 Oppermann H. , Zakel E. , Engelmann G. , Reichl H. : Investigation of Self-Alignment During Flip-Chip Assembly Using Eutectic Gold-Tin Metallurgy, 4th Int. Conf. and Exhibition on Micro Electro, Opto and Mechanical Systems and Components, MST '94.

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