Real-Time Control of a Battery Energy Storage System Using a Reconfigurable Synchrophasor-Based Control System

Abstract

Synchrophasor-driven smart grid applications aiming to orchestrate a diverse set of Distributed Energy Resources (DERs) require extensive infrastructure including substantial instrumentation hardware, communication network extensions and controller installations for coordinated operation. This can make the overall installation expensive. Additionally, due to the computational complexity and data-intensive nature of the PDC functionality, most of the existing PDC implementations are on a purely software level, making them unsuitable for the real-time applications. To address this, the current paper proposes an alternate architecture for the real-time synchrophasor-based control of DER applications (e.g., microgrids) incorporating a centralized synchronization hardware designed to replace aggregation Phasor Data Concentrators (PDCs) and supplementary control algorithms into a singular reconfigurable hardware. This particular hardware is termed a Synchrophasor Synchronization Gateway and Controller (SSGC). The robustness of the proposed architecture is tested by using real-time (RT) Controller Hardware-In-the-Loop (CHIL) simulation-based experiments by manipulating the communication network that connects the SSGC with multiple Phasor Measurement Unit (PMU) streams broadcasting data through the IEEE C37.118.2 protocol in real time. These PMU streams were generated by using a real-time microgrid model running on a Typhoon HIL 604 simulator. To manipulate the communication interface between the proposed SSGC hardware and the PMU streams, a configurable Wide Area Network (WAN) emulator and communication network impairment appliance deployed in the Candela Technologies CT910 external hardware was utilized. The real-time control system was expanded by incorporating a low-pass filter to eliminate the potential overswitching of a Battery Energy Storage System (BESS). The proposed architecture demonstrated a reliable performance under ideal to moderately tampered communication networks. However, under a significantly corrupted network, the performance of this architecture is acutely affected.