Delay Insensitive Ternary CMOS Logic for Secure Hardware-Reference-Cited by-同舟云学术

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Delay Insensitive Ternary CMOS Logic for Secure Hardware

Published:2015-09-11 Issue:3 Volume:5 Page:183-215
ISSN:2079-9268
Container-title:Journal of Low Power Electronics and Applications
language:en
Short-container-title:JLPEA

Author:

Nair Ravi,Smith Scott,Di Jia

Publisher

MDPI AG

Subject

Electrical and Electronic Engineering

Link

http://www.mdpi.com/2079-9268/5/3/183/pdf

Reference164 articles.

1. International Technology Roadmap for Semiconductors—Design, 2003 Editionhttp://www.itrs.net/Links/2003ITRS/Design2003.pdf

2. International Technology Roadmap for Semiconductors—Design, 2007 Editionhttp://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_Design.pdf

3. International Technology Roadmap for Semiconductors—Design, 2012 Editionhttp://www.itrs.net/Links/2012ITRS/Home2012.htm

4. Micropipelines;Sutherland,1989

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3. A dual-rail/single-rail hybrid system using null convention logic circuits;Microelectronics Journal;2022-07

4. Simulation-Based Method for Analyzing Timing Attack Against Pass-Code Breaking System;Lecture Notes in Electrical Engineering;2022

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