Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory
-
Published:2023-11-30
Issue:12
Volume:14
Page:2199
-
ISSN:2072-666X
-
Container-title:Micromachines
-
language:en
-
Short-container-title:Micromachines
Author:
An Ukju1ORCID, Yoon Gilsang1ORCID, Go Donghyun1ORCID, Park Jounghun1ORCID, Kim Donghwi1, Kim Jongwoo1, Lee Jeong-Soo1
Affiliation:
1. Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 37673, Republic of Korea
Abstract
Electrical characteristics with various program temperatures (TPGM) in three-dimensional (3-D) NAND flash memory are investigated. The cross-temperature conditions of the TPGM up to 120 °C and the read temperature (TREAD) at 30 °C are used to analyze the influence of grain boundaries (GB) on the bit line current (IBL) and threshold voltage (VT). The VT shift in the E-P-E pattern is successfully decomposed into the charge loss (ΔVT,CL) component and the poly-Si GB (ΔVT,GB) component. The extracted ΔVT,GB increases at higher TPGM due to the reduced GB potential barrier. Additionally, the ΔVT,GB is evaluated using the Technology Computer Aided Design (TCAD) simulation, depending on the GB position (XGB) and the bit line voltage (VBL).
Funder
Samsung Electronics Ministry of Science and ICT
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference35 articles.
1. 3-D NAND Technology Achievements and Future Scaling Perspectives;Goda;IEEE Trans. Electron Devices,2020 2. Parat, K., and Goda, A. (2018, January 1–5). Scaling Trends in NAND Flash. Proceedings of the 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA. 3. Lee, S., Kim, C., Kim, M., Joe, S.-m., Jang, J., Kim, S., Lee, K., Kim, J., Park, J., and Lee, H.-J. (2018, January 11–15). A 1Tb 4b/cell 64-stacked-WL 3D NAND Flash Memory with 12MB/s Program Throughput. Proceedings of the 2018 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA. 4. Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling;Sanuki;IEEE J. Explor. Solid-State Comput. Devices Circuits,2021 5. Aiba, Y., Tanaka, H., Maeda, T., Sawa, K., Kikushima, F., Miura, M., Fujisawa, T., Matsuo, M., Horii, H., and Mukaida, H. (2021, January 16–19). Bringing in Cryogenics to Storage: Characteristics and Performance Improvement of 3D Flash Memory. Proceedings of the 2021 IEEE International Memory Workshop (IMW), Dresden, Germany.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
|
|