Author:
Vaisband Inna,Friedman Eby G.,Ginosar Ran,Kolodny Avinoam
Subject
Electrical and Electronic Engineering
Reference30 articles.
1. Timing Optimization through Clock Skew Scheduling;Kourtev,2009
2. Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing;Tsai;IEEE Trans. Comput. Aid. Des. Int.,2004
3. Wire sizing for non-tree topology;Li;IEEE Trans. Comput. Aided Des. Int.,2007
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