Analysis of 3D Channel Current Noise in Small Nanoscale MOSFETs Using Monte Carlo Simulation

Abstract

As field effect transistors are reduced to nanometer dimensions, experimental and theoretical research has shown a gradual change in noise generation mechanisms. There are few studies on noise theory for small nanoscale transistors, and Monte Carlo (MC) simulations mainly focus on 2D devices with larger nanoscale dimensions. In this study, we employed MC simulation techniques to establish a 3D device simulation process. By setting device parameters and writing simulation programs, we simulated the raw data of channel current noise for a silicon-based metal–oxide–semiconductor field-effect transistor (MOSFET) with a 10 nm channel length and calculated the drain output current based on these data, thereby achieving static testing of the simulated device. Additionally, this study obtained a 3D potential distribution map of the device channel surface area. Based on the original data from the simulation analysis, this study further calculated the power spectral density of the channel current noise and analyzed how the channel current noise varies with gate voltage, source–drain voltage, temperature, and substrate doping density. The results indicate that under low-temperature conditions, the channel current noise of the 10 nm MOSFET is primarily composed of suppressed shot noise, with the proportion of thermal noise in the total noise slightly increasing as temperature rises. Under normal operating conditions, the channel current noise characteristics of the 10 nm MOSFET device are jointly characterized by suppressed shot noise, thermal noise, and cross-correlated noise. Among these noise components, shot noise is the main source of noise, and its suppression degree decreases as the bias voltage is reduced. These findings are consistent with experimental observations and theoretical analyses found in the existing literature.