High Step-Up Thirteen Level Switched-Capacitor Inverter Topology for HFAC Power System

Abstract

This article proposes two new high-frequency, thirteen-level switched capacitor inverter topologies. Compared with the counterpart existing topologies, which were recently published, the switch count, capacitor voltage, and voltage stress on the switch are reduced. In addition, the proposed topologies have inherited merits such as six-time voltage boosting levels and self-balanced capacitor voltages as well. The capacitor ripple voltages and the proposed topology performance are analyzed. The prototype setup is developed for 500W, and the results are verified. The maximum efficiency is approximately equal to 97.5% for simulation. Furthermore, it is approximately equal to 96.1% for experimental, and both are measured at an output power of 500 W. Finally, the characteristics of the proposed topologies are tested under several scenarios, such as modulation index variations and load changes, and the findings are reported.