Abstract
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference74 articles.
1. Certain Arteris Technology Assets Acquiredhttps://www.arteris.com/press-releases/qualcomm-arteris-asset-acquisition-2013
2. Intel Acquires NetSpeed Systems for Chip Designhttps://newsroom.intel.com/news/intel-acquires-netspeed-systems-chip-design/#gs.i08tpn
3. Facebook Buys Interconnect IP Vendor Sonicshttps://www.eetimes.com/facebook-buys-interconnect-ip-vendor-sonics/
4. Epiphany-v: A 1024 processor 64-bit risc system-on-chip;Olofsson;arXiv,2016
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