Formal Chaos Existing Conditions on a Transmission Line Circuit with a Piecewise Linear Resistor

Abstract

By using one-dimensional (1-D) map methods, some lossless transmission line circuits with a short at one side terminal have been actively studied. Bifurcation results or chaotic states in the circuits have been reported. On the other hand, many weak or strong definitions such that a 1-D map is mathematically chaotic are still being studied. In such definitions, the definition of formal chaos is well known as being the most traditional and most definite. However, formal chaos existences have not been rigorously proven in such circuits. In this paper, a general lossless transmission circuit is considered first with a dc bias voltage source in series with a load resistor at one side terminal and with a three-segment piecewise linear resistor at another side terminal. Secondly, the method for deriving a 1-D map describing the behavior of the circuit is summarized. Thirdly, to provide a basis of chaotic application for the 1-D map, the mathematical definition of formal chaos and the sufficient conditions of the existence of formal chaos are discussed. Furthermore, by using Maple, formal chaos existences and bifurcation behavior of 1-D maps are presented. By using the Lyapunov exponent, the observability of formal chaos in such bifurcation processes is outlined. Finally, the principal results and the future works are summarized.