Three-Dimensional Integrated Fan-Out Wafer-Level Package Micro-Bump Electromigration Study
-
Published:2023-06-15
Issue:6
Volume:14
Page:1255
-
ISSN:2072-666X
-
Container-title:Micromachines
-
language:en
-
Short-container-title:Micromachines
Author:
Tian Wenchao12, Gao Ran1, Gu Lin3, Ji Haoyue23, Zhou Liming4
Affiliation:
1. Hangzhou Institute of Technology, Xidian University, Hangzhou 311231, China 2. School of Electro-Mechnical Engineering, Xidian University, Xi’an 710071, China 3. Zhongkexin Integrated Circuit Co., Wuxi 214035, China 4. Yangzhou Yangjie Electronic Technology Co., Ltd., Yangzhou 225008, China
Abstract
To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2.
Funder
China Postdoctoral Science Foundation
Subject
Electrical and Electronic Engineering,Mechanical Engineering,Control and Systems Engineering
Reference40 articles.
1. Tian, W., Li, B., Li, Z., Cui, H., Shi, J., Wang, Y., and Zhao, J. (2022). Using Chiplet Encapsulation Technology to Achieve Processing-in-Memory Functions. Micromachines, 13. 2. Chang, K.T., Huang, C., Kuo, H., Jhong, M., Hsieh, T., Hung, M., and Wang, C. (2019, January 28–31). Ultra High Density IO Fan-Out Design Optimizationwith Signal Integrity and Power Integrity. Proceedings of the 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA. 3. Chong, C.T., Guan, L.T., Ho, D., Choong, C.S., Faxing, C., and Bhattacharya, S. (2018, January 4–7). High Density Interconnection for Heterogeneous Integration on FOWLP Platform. Proceedings of the 2018 IEEE 20th Electronics Packaging Technology Conference (EPTC), Singapore. 4. Zhu, J., Ming, X., and Yao, X. (2018, January 8–11). Research on Key Process Technology of RDL-first Fan-out Wafer Level Packaging. Proceedings of the 2018 19th International Conference on Electronic Packaging Technology (ICEPT), Shanghai, China. 5. Beth, K., and Kroehnert, S. (2019). Advances in Embedded and Fan-Out Wafer Level Packaging Technologies, John Wiley & Sons.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A process method for making BGA solder mask using nickel oxide;2023 IEEE International Workshop on Electromagnetics: Applications and Student Innovation Competition (iWEM);2023-07-15
|
|