Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

Abstract

In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of pages. Increasing the number of stacks increases the number of cells that are erased at one time, which can lead to undesirable durability degradation. In this case, the sub-block erase operation can reduce the burden on the cell by up to half, due to the erase operation. The distribution of the hole density (hDensity) and the potential, according to VDummy, was analyzed when block1 and block2 were erased by setting WL0:WL7 to block1, WL9:WL15 to block2, and WL8 to dummy WL. For the simulation results, block1 showed an optimal distribution of hDensity and potential in the order of 20 V, floating, and 0 V. In block2, the optimal distribution of hDensity was shown in the order of 20 V, floating, and 0 V, with the optimal distribution of the potential in the order of floating and 0 V.