Use of Threshold Median Adjustment to Achieve Accurate Current Balancing of Interleaved Buck Converter with Constant Frequency Hysteresis Control
-
Published:2024-09-04
Issue:17
Volume:13
Page:3521
-
ISSN:2079-9292
-
Container-title:Electronics
-
language:en
-
Short-container-title:Electronics
Author:
Lu Liangliang1, Li Qidong1, Yang Yuxiang1, Huang Yuchao2, Li Zeli1, Zhang Desheng2ORCID
Affiliation:
1. School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China 2. School of Automation, Wuhan University of Technology, Wuhan 430074, China
Abstract
This paper proposes a current balancing loop that is obtained using the threshold median adjustment (TMA-CBL) to achieve the accurate current balancing of an interleaved constant frequency hysteresis (CFH) buck converter. The CFH control is implemented with a frequency phase loop based on a threshold width adjustment (TWA-FPL). To ensure the loop’s stability and minimize the steady-state error, a multi-phase, coupled, small-signal model (MPC-SSM) is derived with a consideration of the coupling effect among the multiple phases. Furthermore, the current balancing error is analyzed in detail, with a consideration of the sensing resistance deviations in the loop. Finally, based on a 180 nm BCD process, a four-phase interleaved buck converter is fabricated to verify the effectiveness of the proposed TMA-CBL. The maximum current balancing error is within 0.68% when the sensing resistors are deviated by 5%.
Funder
State Administration of Science, Technology and Industry for National Defence of the People’s Republic of China National Natural Science Foundation of China
Reference26 articles.
1. Burton, E.A., Schrom, G., Paillet, F., Douglas, J., Lambert, W.J., Radhakrishnan, K., and Hill, M.J. (2014, January 16–20). FIVR—Fully integrated voltage regulators on 4th generation Intel® Core™ SoCs. Proceedings of the 2014 IEEE Applied Power Electronics Conference and Exposition—APEC 2014, Fort Worth, TX, USA. 2. Bharath, K., and Venkataraman, S. (June, January 31). Power Delivery Design and Analysis of 14nm Multicore Server CPUs with Integrated Voltage Regulators. Proceedings of the 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA. 3. Fukuoka, T., Karasawa, Y., Akiyama, T., Oka, R., Ishida, S., Shirasawa, T., Sonehara, M., Sato, T., and Miyaji, K. (2019, January 17–21). An 86% Efficiency, 20MHz, 3D-Integrated Buck Converter with Magnetic Core Inductor Embedded in Interposer Fabricated by Epoxy/Magnetic-Filler Composite Build-Up Sheet. Proceedings of the 2019 IEEE Applied Power Electronics Conference and Exposition (APEC), Anaheim, CA, USA. 4. Ain, Q.u., Basim, M., Shah, S.A.A., and Lee, K.Y. (2022, January 19–22). A Design of high-efficiency Constant On-Time Control DC-DC Buck Converter for Power Management integrated circuits. Proceedings of the 2022 19th International SoC Design Conference (ISOCC), Gangneung-si, Republic of Korea. 5. Li, P., Bashirullah, R., Hazucha, P., and Karnik, T. (2007, January 14–16). A Delay Locked Loop Synchronization Scheme for High Frequency Multiphase Hysteretic DC-DC Converters. Proceedings of the 2007 IEEE Symposium on VLSI Circuits, Kyoto, Japan.
|
|