Affiliation:
1. School of Microelectronics, Tianjin University, Tianjin 300072, China
2. Beijing Zhixin Microelectronics Technology Co., Ltd., Beijing 100192, China
Abstract
This paper analyzes the underlying logic of the processor’s behavior level code. It proposes an automatic model construction and formal verification method for the cache consistency protocol with the aim of ensuring data consistency in the processor and the correctness of the cache function. The main idea of this method is to analyze the register transfer level (RTL) code directly at the module level and variable level, and extract the key modules and key variables according to the code information. Then, based on key variables, conditional behavior statements are retrieved from the code, and unnecessary statements are deleted. The model construction and simplification of related core states are completed automatically, while also simultaneously generating the attribute library to be verified, using “white list” as the construction strategy. Finally, complete cache consistency protocol verification is implemented in the model detector UPPAAL. Ultimately, this mechanism reduces the 142 state-transition path-guided global states of the cache module to be verified into 4 core functional states driven by consistency protocol implementation, effectively reducing the complexity of the formal model, and extracting 32 verification attributes into 6 verification attributes, reducing the verification time cost by 76.19%.
Funder
National Key Research and Development Plan of China
National Natural Science Foundation of Tianjin City
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Reference35 articles.
1. Harika, J., Baleeshwar, P., Navya, K., and Shanmugasundaram, H. (2022, January 9–11). A review on artificial intelligence with deep human reasoning. Proceedings of the 2022 International Conference on Applied Artificial Intelligence and Computing (ICAAIC), Salem, India.
2. Bhari, S., and Quraishi, S.J. (2022, January 26–27). Blockchain and cloud computing-a review. Proceedings of the 2022 International Conference on Machine Learning, Big Data, Cloud and Parallel Computing (COM-IT-CON), Faridabad, India.
3. Rahman, M.M. (2012, January 18–19). Process synchronization in multiprocessor and multi-core processor. Proceedings of the 2012 International Conference on Informatics, Electronics & Vision (ICIEV), Dhaka, Bangladesh.
4. Kostadinov, A.N., and Kouzaev, G.A. (2022, October 15). A novel processor for artificial intelligence acceleration. Available online: https://api.semanticscholar.org/CorpusID:250237892.
5. Cmos-integrated memristive non-volatile computing-in-memory for ai edge processors;Chen;Nat. Electron.,2019