Writing productive stencil codes with overlapped tiling-Reference-Cited by-同舟云学术

Writing productive stencil codes with overlapped tiling

Published:2009-01 Issue:1 Volume:21 Page:25-39
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat.: Pract. Exper.

Author:

Guo Jia,Bikshandi Ganesh,Fraguela Basilio B.,Padua David

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference23 articles.

1. Organizing matrices and matrix operations for paged memory systems;McKellar;Communications of the ACM,1969

2. Bikshandi G, Guo J, Hoeflinger D, Almasi G, Fraguela BB, Garzarán MJ, Padua D, von Praun C. Programming for parallelism and locality with hierarchically tiled arrays. Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'06), New York, NY, U.S.A., 2006; 48-57.

3. Bikshandi G, Guo J, von Praun C, Tanase G, Fraguela BB, Garzarán MJ, Padua D, Rauchwerger L. Design and use of htalib-A library for hierarchically tiled arrays. Proceedings of the International Workshop on Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science (LNCS), vol. 4382, New Orleans, LA, U.S.A., November 2006; 17-32.

4. Guo J, Bikshandi G, Fraguela BB, Garzarán MJ, Padua D. Programming with tiles. Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'08), Salt Lake City, UT, U.S.A., February 2008; 111-122.

5. NAS Parallel Benchmarks. Website. http://www.nas.nasa.gov/Software/NPB/ [22 September 2007].

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Adapting combined tiling to stencil optimizations on sunway processor;CCF Transactions on High Performance Computing;2023-05-17

2. Efficient Task-Mapping of Parallel Applications Using a Space-Filling Curve;Proceedings of the International Conference on Parallel Architectures and Compilation Techniques;2022-10-08

3. Architectural Adaptation and Performance-Energy Optimization for CFD Application on AMD EPYC Rome;IEEE Transactions on Parallel and Distributed Systems;2021-12-01

4. Optimizing Stencil Codes with Exploiting Data Reuse;2021 International Conference on Information Control, Electrical Engineering and Rail Transit (ICEERT);2021-10

5. Automatic Code Generation and Optimization of Large-scale Stencil Computation on Many-core Processors;50th International Conference on Parallel Processing;2021-08-09