Performance control for interconnection of identical systems: Application to PLL network design-Reference-Cited by-同舟云学术

Performance control for interconnection of identical systems: Application to PLL network design

Published:2014-12-29 Issue:1 Volume:26 Page:3-27
ISSN:1049-8923
Container-title:International Journal of Robust and Nonlinear Control
language:en
Short-container-title:Int. J. Robust. Nonlinear Control

Author:

Korniienko Anton¹²^ORCID,Scorletti Gerard²,Colinet Eric¹,Blanco Eric²

Affiliation:

1. CEA, LETI, MINATEC; 17 rue des martyrs; 38054 Grenoble Cedex 9 France

2. Laboratoire Ampère; Ecole Centrale de Lyon; 36 Av. Guy de Collongue 69134 Ecully Cedex France

Funder

Agence Nationale de la Recherche

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Mechanical Engineering,Aerospace Engineering,Biomedical Engineering,General Chemical Engineering,Control and Systems Engineering

Link

http://onlinelibrary.wiley.com/wol1/doi/10.1002/rnc.3285/fullpdf

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4. Saint-Laurent M Swaminathan M A multi-PLL clock distribution architecture for gigascale integration Proc. IEEE Computer Society Workshop on VLSI Washington 2001 30 35

5. Korniienko A Colinet E Scorletti G Blanco E Galayko D Juillard J A clock network of distributed ADPLLs using an asymmetric comparison strategy Proc. Int. Symposium Circuits and Systems Paris 2010 3212 3215

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