Architecture design of high-efficient and non-memory AES crypto-core for WPAN-Reference-Cited by-同舟云学术

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Architecture design of high-efficient and non-memory AES crypto-core for WPAN

Published:2010-06-24 Issue:12 Volume:23 Page:1332-1347
ISSN:1532-0626
Container-title:Concurrency and Computation: Practice and Experience
language:en
Short-container-title:Concurrency Computat.: Pract. Exper.

Author:

Chen Rong-Jian,Lin Jun-Jian,Hung Su-Min,Lai Jui-Lin,Horng Shi-Jinn

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference25 articles.

1. IEEE 802.15 WPAN Task Group 1 (TG1) http://www.ieee802.org/15/pub/TG1.html 2010

2. IEEE 802.15 WPAN ™ Task Group 4 (TG4) http://www.ieee802.org/15/pub/TG4.html 2010

3. IEEE 802.15 WPAN Task Group 3 (TG3) http://www.ieee802.org/15/pub/TG3.html 2010

4. IEEE 802.15 WPAN High Rate Alternative PHY Task Group 3a (TG3a) http://www.ieee802.org/5/pub/TG3a.html 2010

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power efficient and high performance VLSI architecture for AES algorithm;Journal of Electrical Systems and Information Technology;2015-09

2. Design CAROM Module Used in AES Structure for Sub-byte and Inv-sub-byte Transformation;2013 International Symposium on Biometrics and Security Technologies;2013-07

3. Special Issue: Securing Distributed Networks and Systems;Concurrency and Computation: Practice and Experience;2011-03-08

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