Considerations of ultrahigh-speed, low-power active pull-down NTL logic circuits-Reference-Cited by-同舟云学术

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Considerations of ultrahigh-speed, low-power active pull-down NTL logic circuits

Published:1992 Issue:8 Volume:75 Page:72-82
ISSN:8756-663X
Container-title:Electronics and Communications in Japan (Part II: Electronics)
language:en
Short-container-title:Electron. Comm. Jpn. Pt. II

Author:

Usami Mitsuo,Nakamura Tohru,Shiozawa Noboru,Tanabe Masamichi,Mandai Takahiro

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy

Reference16 articles.

1. , , , and . A 100-k gate ECL standard-cell LSI with layout system. ISSCC Tech. Dig., pp. 94–95 (Feb. 1990).

2. , and . A 13,000-gate, three-layer metal bipolar gate array. IEEE Custom Integrated Circuits Conference, pp. 20.1.1–3 (Apr. 1988).

3. A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage

4. and . High-speed, low-power, charge-buffered, active pull-down ECL circuit. IEEE Bipolar Circuits and Technology Meeting, pp. 132–135 (Sept. 1990).

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications;IEEE Journal of Solid-State Circuits;1995-06

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