Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models

Author:

Yang Ping,Li Wei

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Science Applications,Modeling and Simulation

Reference6 articles.

1. Johnson ZE, Schneck NR, Thoreson AR et al. Thermo-mechanical simulation of stacked chip scale packages with Moiré interferometry validation. Thermomechanical Phenomena in Electronic Systems-Proceedings of the Intersociety Conference, v 2006, Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena and Emerging Technologies in Electronic Systems, ITherm 2006, San Diego, CA, USA, 2006; 1120-1125.

2. Thermal cycling analysis of flip-chip solder joint reliability;Pang;IEEE Transactions on Component and Package Technologies,2001

3. Chip scale package (CSP) solder joint reliability and modeling;Amagai;Microelectronics Reliability,1999

4. Sliding simulation for adhesion problems in micro gear trains based on an atomistic simplified model;Yang;Microsystem Technologies,2006

5. Research on parametric analysis for stress of PBGA solder joint under shock load;Yang;International Journal of Materials and Product Technology,2008

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