High‐Yield Production of High‐κ/Metal Gate Nanopattern Array for 2D Devices via Oxidation‐Assisted Etching Approach

Author:

Hong Weida12,Zhang Jiejun12,Zeng Daobing12,Wang Chen12,Xue Zhongying1,Zhang Miao1,Tian Ziao1,Di Zengfeng1ORCID

Affiliation:

1. State Key Laboratory of Materials for Integrated Circuits Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai 200050 China

2. Center of Materials Science and Optoelectronics Engineering University of Chinese Academy of Sciences Beijing 100049 China

Abstract

Abstract2D materials with atomically thin nature are promising to develop scaled transistors and enable the extreme miniaturization of electronic components. However, batch manufacturing of top‐gate 2D transistors remains a challenge since gate dielectrics or gate electrodes transferred from 2D material easily peel away as gate pitch decreases to the nanometer scale during lift‐off processes. In this study, an oxidation‐assisted etching technique is developed for batch manufacturing of nanopatterned high‐κ/metal gate (HKMG) stacks on 2D materials. This strategy produces nano‐pitch self‐oxidized Al2O3/Al patterns with a resolution of 150 nm on 2D channel material, including graphene, MoS2, and WS2 without introducing any additional damage. Through a gate‐first technology in which the Al2O3/Al gate stacks are used as a mask for the formation of source and drain, a short‐channel HKMG MoS2 transistor with a nearly ideal subthreshold swing (SS) of 61 mV dec−1, and HKMG graphene transistor with a cut‐off frequency of 150 GHz are achieved. Moreover, both graphene and MoS2 HKMG transistor arrays exhibit high uniformity. The study may bring the potential for the massive production of large‐scale integrated circuits using 2D materials.

Funder

National Natural Science Foundation of China

Science and Technology Commission of Shanghai Municipality

Publisher

Wiley

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