7‐2: Invited Paper: A 40 nm Gate Length Surrounding Gate Vertical‐Channel FET Using Thermally Stable In‐Al‐Zn‐O Channel for 3D CMOS‐LSI Applications

Author:

Sato Yuta1,Fujiwara Hirokazu1,Saito Nobuyoshi1,Ueda Tomomasa1,Ikeda Keiji1

Affiliation:

1. Institute of Memory Technology Research & Development Kioxia Corporation Japan

Publisher

Wiley

Reference11 articles.

1. Material characteristics and applications of transparent amorphous oxide semiconductors;Kamiya T.;NPG Asia Mater,2010

2. Highly Reliable BEOL-Transistor with Oxygen-controlled InGaZnO and Gate/Drain Offset Design for High/Low Voltage Bridging I/O Operations;Kaneko K.;2011 IEEE International Electron Devices Meeting (IEDM)

3. Experimental demonstration of ferroelectric HfO2 FET with ultrathin-body IGZO for high-density and low-power memory application;Mo F.;2019 Symposium on VLSI Technology: Digest of Technical papers

4. 3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm;Oota M.;2019 IEEE International Electron Devices Meeting (IEDM)

5. Channel shortening phenomenon due to redox reaction in a lateral direction on In-Ga-Zn-O thin film transistors;Kitakado H.;Jpn. J. Appl. Phys.,2012

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