Design and implementation of a scalable switch architecture for efficient high-speed data multicasting-Reference-Cited by-同舟云学术

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Design and implementation of a scalable switch architecture for efficient high-speed data multicasting

Published:2007 Issue:9 Volume:20 Page:1011-1036
ISSN:1074-5351
Container-title:International Journal of Communication Systems
language:en
Short-container-title:Int. J. Commun. Syst.

Author:

Li Cheng,Venkatesan R.,Heys Howard M.

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications

Reference26 articles.

1. , , , . On the throughput of input-queued cell-based switches with multicast traffic. Proceedings of IEEE INFOCOM2001, Alaska, U.S.A., 22–26 April 2001.

2. Scalable electronic packet switches

3. Canadian Microelectronics Corporation (CMC) website: www.cmc.ca.

4. Design of a broadcast packet switching network

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Architecture design, performance analysis and VLSI implementation of a reconfigurable shared buffer for high-speed switch/router;International Journal of Communication Systems;2009-02

2. Performance Modeling of a Reconfigurable Shared Buffer for High-Speed Switch/Router;2008 IEEE International Conference on Communications;2008

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