Synergistic Engineering of Top Gate Stack for Low Hysteresis 2D MoS2 Transistors

Abstract

Abstract2D semiconductors have emerged as candidates for next‐generation electronics. However, previously reported 2D transistors which typically employ the gate‐first process to fabricate a back‐gate (BG) configuration while neglecting the thorough impact on the dielectric capping layer, are severely constrained in large‐scale manufacturing and compatibility with complementary metal–oxide–semiconductor (CMOS) technology. In this study, dual‐gate (DG) field‐effect transistors have been realized based on wafer‐scale monolayer MoS2 and the gate‐last processing, which avoids the transfer process and utilizes an optimized top‐gate (TG) dielectric stack, rendering it highly compatible with CMOS technology. Subsequently, the physical mechanism of TG dielectric deposition and the corresponding controllable threshold voltage (VTH) shift is investigated. Then the fabricated TG‐devices with a large on/off ratio up to 1.7 × 109, negligible hysteresis (≈14 mV), and favorable stability. Additionally, encapsulated TG structured photodetectors have been demonstrated which exhibit photo responsivity (R) up to 9.39 × 103 A W−1 and detectivity (D*) ≈2.13 × 1013 Jones. The result paves the way for future CMOS‐compatible integration of 2D semiconductors for complex multifunctional IC applications.