Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET
Author:
Affiliation:
1. Department of Electronics and Communication Engineering/Applied Sciences Jamia Millia Islamia (Central University) New Delhi India
2. Department of Electrical Engineering, College of Engineering Taif University Taif Saudi Arabia
Publisher
Wiley
Subject
Electrical and Electronic Engineering,Computer Science Applications,Modeling and Simulation
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1002/jnm.2877
Reference50 articles.
1. Analysis of InAs vertical and lateral band-to-band tunneling transistors: Leveraging vertical tunneling for improved performance
2. Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets
3. Counterdoped Pocket Thickness Optimization of Gate-on-Source-Only Tunnel FETs
4. A High-Performance Inverted-C Tunnel Junction FET With Source–Channel Overlap Pockets
5. Source-all-around tunnel field-effect transistor (SAA-TFET): proposal and design
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2. Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET;Physica Scripta;2023-11-28
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4. Drain current model for a hetero‐dielectric single gate tunnel field effect transistor ( HDSG TFET );International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2021-12-14
5. Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2021-03-15
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