P‐9.3: A Typical Interconnect Model for High Bandwidth Video Streaming Transmission in Mixed‐Reality Devices

Abstract

The design of system architecture that incorporates a System‐on‐chip (SoC) and a co‐processor, has emerged as a prevailing trend in the realm of Mixed‐Reality (MR) devices. The interconnection between such two chips is critical for the performance and reliability of MR devices, but it faces challenges from high bandwidth requirement and various channel losses in different chip placements. In this paper, we present a typical chip‐to‐chip interconnect model that can support 32Gbps bandwidth and adapt to various channel loss and transmission line lengths in different system designs. The interconnect model incorporates each typical element in packages, PCB and FPC. We optimize the interconnect model in signal integrity, use the model to simulate the interconnection up to 400mm‐length with calibrated material properties and analyze its performance in time‐domain and frequency‐domain. Our model can offer valuable insight for interconnect design when incorporating a co‐processor approach into MR devices.