Affiliation:
1. School of Electrical Engineering Graduate School of Semiconductor Technology Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak‐ro, Yuseong‐gu Daejeon 34141 Republic of Korea
2. Department of Nanotechnology and Advanced Materials Engineering Sejong University 209 Neungdong‐ro, Gwangjin‐gu Seoul 05006 Republic of Korea
3. Department of Chemical and Biomolecular Engineering Graphene/2D Materials Research Center Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak‐ro, Yuseong‐gu Daejeon 34141 Republic of Korea
4. School of Electronics and Electrical Engineering Dankook University Gyeonggi 16890 Republic of Korea
Abstract
AbstractElectrolyte‐gated synaptic transistors (EGSTs) have attracted considerable attention as synaptic devices owing to their adjustable conductance, low power consumption, and multi‐state storage capabilities. To demonstrate high‐density EGST arrays, 2D materials are recommended owing to their excellent electrical properties and ultrathin profile. However, widespread implementation of 2D‐based EGSTs has challenges in achieving large‐area channel growth and finding compatible nanoscale solid electrolytes. This study demonstrates large‐scale process‐compatible, all‐solid‐state EGSTs utilizing molybdenum disulfide (MoS2) channels grown through chemical vapor deposition (CVD) and sub‐30 nm organic‐inorganic hybrid electrolyte polymers synthesized via initiated chemical vapor deposition (iCVD). The iCVD technique enables precise modulation of the hydroxyl group density in the hybrid matrix, allowing the modulation of proton conduction, resulting in adjustable synaptic performance. By leveraging the tunable iCVD‐based hybrid electrolyte, the fabricated EGSTs achieve remarkable attributes: a wide on/off ratio of 109, state retention exceeding 103, and linear conductance updates. Additionally, the device exhibits endurance surpassing 5 × 104 cycles, while maintaining a low energy consumption of 200 fJ/spike. To evaluate the practicality of these EGSTs, a subset of devices is employed in system‐level simulations of MNIST handwritten digit recognition, yielding a recognition rate of 93.2%.
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2 articles.
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