Design and optimization of a fault‐tolerant demultiplexer based on nano‐scale quantum‐dots

Abstract

AbstractIn quantum electronics, quantum‐dot cellular automata (CA) is a technology to replace current transistor‐based technologies. It provides low‐power, incredibly dense, and high‐speed constructions at a nano‐scale. Quantum‐dot CA is a revolutionary nano‐scale technology that overcomes various restrictions in metal‐oxide technology and simplifies the construction of digital integrated circuits. On the other hand, the demultiplexer is a valuable component for optimizing the entire process in logical design. So, proper cell placement and associated clock zone become the most important design requirement for effective logic operation in demultiplexer. Also, redundancy in fault‐tolerant circuits can increase the dependability of digital circuits. However, in this area, the studies are not adequate, and most of them suffer from improper use of clocking systems and inefficient circuit features such as fault‐tolerant. As a result, the current study demonstrates a unique quantum‐dot CA‐based fault‐tolerant 1:2 demultiplexer design. The proposed method is verified by implementing the fault‐tolerant gates and cell redundancy. Also, we look at the layouts' cells, area, latency, single‐cell missing, single‐cell displacement, and additional single‐cell. We also use the famous simulator, QCADesigner, to model the proposed design. The proposed fault‐tolerant 1:2 demultiplexer's effectiveness is also discussed. Sixty‐eight cells and 0.04 μm2 of occupied space make up the unique fault‐tolerant 1:2 demultiplexer. The results showed that the proposed design is completely faults‐tolerance regarding tolerant missing, displaced, and additional single cells faults.