FPGA implementation of AES algorithm for high throughput using folded parallel architecture-Reference-Cited by-同舟云学术

FPGA implementation of AES algorithm for high throughput using folded parallel architecture

Author:

Rahimunnisa K.¹,Karthigaikumar P.¹,Rasheed Soumiya¹,Jayakumar J.²,SureshKumar S.³

Affiliation:

1. Department of Electronics and Communication Engineering; Karunya University; Coimbatore India

2. Department of Electrical and Electronics Engineering; Karunya University; Coimbatore India

3. Department of Electronics and Communication Engineering; Dr. NGP Institute of Technology; Coimbatore India

Publisher

Wiley

Subject

Computer Networks and Communications,Information Systems

Link

Reference42 articles.

1. Federal Information Processing Standards Publication 197 November 26 2001

2. Hardware implementation of AES algorithm;Mali;Journal of Electrical Engineering,2005

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