A 600 GHz varactor frequency multiplier using 65-nm CMOS technology

Author:

Choi S.H.1ORCID,Yi C.1ORCID,Kim M.1

Affiliation:

1. School of Electrical Engineering; Korea University; Seoul 02841 Republic of Korea

Funder

Institute for Information & communications Technology Promotion (IITP)

Korean government (MSIP)

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference6 articles.

1. A 122 GHz phase-locked loops in 65-nm CMOS technology;Kim;IEEE Trans Microwave Theory Tech.,2016

2. A high-power broadband passive terahertz frequency doubler in CMOS;Han;IEEE Trans Microwave Theory Tech.,2013

3. An RF model of the accumulation-mode MOS varactor valid in both accumulation and depletion regions;Song;IEEE Trans Electron Devices.,2003

4. An active 600 GHz frequency multiplier-by-six S-MMIC;Lewark;IEEE Mtt-S.,2013

5. 600 GHz InP HBT frequency multiplier;Choi;Electron Lett.,2015

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Research and Design of Frequency Quadrupler Based on CMOS;Lecture Notes in Electrical Engineering;2023

2. Design and simulation analysis of THz wave parabolic antenna with beam deflection;International Journal of RF and Microwave Computer-Aided Engineering;2021-02-18

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