Reconfigurable FIFO memory circuit for synchronous and asynchronous communication-Reference-Cited by-同舟云学术

Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

Author:

Abdel‐hafeez Saleh¹²^ORCID,Gordon‐Ross Ann³

Affiliation:

1. Department of Computer Engineering Jordan University of Science and Technology Irbid Jordan

2. Sabbatical at Department of Computer Engineering, College of Computer Qassim University Qassim Buraydah Saudi Arabia

3. Department of Electrical and Computer Engineering University of Florida (UF) Gainesville Florida USA

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Link

Reference34 articles.

3. A current‐sensed high‐speed and low‐power first‐in‐first‐out memory using a Wordline/Bitline‐swapped dual‐port SRAM cell;Shibata N;IEEE j SSC,2002

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

3. Design & Implementation of Novel Asynchronous FIFO;2023 IEEE International Symposium on Smart Electronic Systems (iSES);2023-12-18