P‐7.4: Influence of Annealing on Electrical Properties of ITO‐Decapped a‐Si:H TFT

Abstract

The thin‐film transistors based on hydrogenated amorphous silicon (a‐Si:H TFTs) undergone ITO‐Decap process usually occur a significant degradation of the device performance after the annealing treatment, especially the on‐state current (Ion). It is valuable to illuminate the cause and to get a way to solve the Ion drop problem induced by ITO‐Decap. In present work, three sets of the a‐Si:H TFTs with ITO common electrode were fabricated, and undergone different Dacap and annealing treatment. The effect of annealing times on the electrical properties and content depth distribution of O, In and Si elements in ITO‐Decapped samples were investigated experimentally and theoretically. It is found the carrier concentration decrease, but the resistivity increases with the increase of annealing times. The invasion of impurity O and In ions is the key factor to cause the device performance degradation. The theoretical simulation indicates that the invaded In atoms would bond with P to generate In‐P compound to reduce the carrier concentration, and the invaded O atoms would form SiOX oxide to enahnce the contact resistance. These two negative influences can account for the poor electrical properties of the annealed samples and the worse trend with the increase of annealing times.