Degradation Analysis of Chaotic Systems and their Digital Implementation in Embedded Systems

Abstract

Digital implementation of chaotic systems (CSs) has attracted increasing attention from researchers due to several applications in engineering, e.g., in areas as cryptography and autonomous mobile robots, where the properties of chaotic systems are strongly related. The CSs in the continuous version (CV) need to be discretized where chaotic degradation must be analyzed to guarantee preservation of chaos. In this paper, we present a degradation analysis of five three-dimensional CSs and the necessary conditions to implement the discretized versions (DVs) of Lorenz, Rössler, Chen, Liu and Chen, and Méndez-Arellano-Cruz-Martínez (MACM) CSs. Analytical and numerical analyses of chaos degradation are conducted by using the time series method; the maximum discrete step size and the Lyapunov Exponents (LEs) are computed by using the Euler, Heun, and fourth-order Runge–Kutta (RK4) numerical algorithms (NAs). We conducted comparative studies of performance based on time complexity of the five proposed CSs in their DVs by using four embedded systems (ESs) based on three families of Microchip microcontrollers 8-bit PIC16F, 16-bit dsPIC33FJ, and 32-bit PIC32MZ (of low-cost electronic implementation) and a Field Programmable Gate Array (FPGA). Based on the results, the intervals at control parameters to guarantee chaos are proposed, which improves the performance characteristics of the five proposed CSs in their DVs based on digital applications.