Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures
Author:
Affiliation:
1. Dept. of E&C, VTU, Belgaum 5900018, India
2. Dept. of ETC, IIIT-BH, Bhubaneswar 751003, India
3. Dept. of ECE, ASCET, Gudur 524101, India
Abstract
Publisher
Hindawi Limited
Subject
Electrical and Electronic Engineering,Instrumentation,Control and Systems Engineering
Link
http://downloads.hindawi.com/journals/js/2022/2911777.pdf
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Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Retracted: Integrated Sensory Throughput and Traffic-Aware Arbiter for High Productive Multicore Architectures;Journal of Sensors;2023-12-13
2. Communication Latency and Power Consumption Consequence in Multi-Core Architectures and Improvement Methods;International Journal of Electrical and Electronics Research;2023-03-30
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