A Multineuron-Based Routing Algorithm of Tile-Based 2-D Mesh

Abstract

Tile-based architecture is broadly utilized in the structuring of the system-on-chip by different vendors. Nevertheless, the performance of the system-on-chip (SoC) is incredibly influenced by the performance of the network hidden on a chip named network-on-chip (NoC). Routing of network-on-chip network chips plays a crucial role in the overall performance of the NoC. In this paper, we have proposed a routing algorithm that utilizes the neural network to perform the routing. This routing algorithm updates the route dependent on the port execution of the switch. From the outcome, the execution of the directing has worked successfully and has the option to deal with the enormous burden viably. The result obtained shows that the performance metric for the uniform traffic is slightly better in comparison to XY routing at the higher loads of 80%. In the case of neighbor traffic, bit complement traffic, and tornado traffic, these values are higher on 80% of the load. The reason for better handling of the loads is due to the parallelization due to the pipeline created by the neural network routing decision.