Parallel Jacobi EVD Methods on Integrated Circuits

Author:

Sun Chi-Chia1,Götze Jürgen2,Jan Gene Eu3

Affiliation:

1. Department of Electrical Engineering, National Formosa University, Wunhua Road 64, Huwei 632, Taiwan

2. Information Processing Lab, Technology University of Dortmund, Otto-Hahn-Strase 4, 44221 Dortmund, Germany

3. Institute of Electrical Engineering, National Taipei University, University Road 151, San Shia District, New Taipei City 23741, Taiwan

Abstract

Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

Funder

National Science Council

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

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