Analysis of Negative to Positive Differential Conductance Transition in NCFET and Guidelines for Analog Circuit Designing

Abstract

In this chapter, we explained a detailed physical insight of Negative Differential Resistance (NDR) to Positive Differential Resistance (PDR) transition in a ferroelectric-based negative capacitance (NC) FET and its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on FDSOI NCFET. The NDR to PDR transition occurs due to the Ferroelectric (FE) layer capacitance changes from a negative to a positive state during channel pinch-off. This, in turn, results in a valley point in the output characteristic (IDS-VDS) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical Electric field through the FE layer in the channel pinch-off region using body bias (VBB). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge resulted in a faster NDR to PDR transition. Further, we have utilized the modulation in NDR to PDR transition due to VBack for designing a current mirror. Results show that the output current (IOUT) variation due to VDS, reduces from ~8% to ~2% with VBack. We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS-VDS. We have also explored the device scaling effect on the amplifier gain and found that ~2.23x gain can be increased with a smaller channel length and higher device width.