Architecture design for regulating and scheduling user's traffic in ATM networks

Abstract

The asynchronous transfer mode (ATM) technique provides a standardized and flexible scheme to transport and switch traffic effectively for different services. To provide satisfactory quality of service (QOS) to all users on the network, it is necessary to control the user's traffic so that network resources can be efficiently and fairly utilized by all the users while still meeting the individual QOS requirement. In this paper, we propose to control the user's traffic at two places in the network: at the user-network interface (UNI) by a traffic shaper or a traffic enforcer, and at the network-node interface (NNI) by a traffic regulator and a traffic scheduler. The traffic shaper/enforcer adopted in our work contains a buffer to delay and shape the violating cells that do not comply with some agreed-upon traffic parameters. The traffic regulator regulates cells at each network node to avoid long bursts being formed which may increase the network congestion probability. A traffic scheduler that follows the traffic regulator schedules the cells' departure sequences based on their delay priorites. We have proposed a general, feasible architecture to implement the traffic shaper, regulator, and scheduler, at various places in the network. A key component, the Sequencer chip, which contains 150k CMOS transistors, has been implemented to realize the architecture.