SimNet

Author:

Li Lingda1,Pandey Santosh2,Flynn Thomas1,Liu Hang2,Wheeler Noel3,Hoisie Adolfy1

Affiliation:

1. Brookhaven National Laboratory, Upton, NY, USA

2. Stevens Institute of Technology, Hoboken, NJ, USA

3. Laboratory for Physical Sciences, College Park, MD, USA

Abstract

While cycle-accurate simulators are essential tools for architecture research, design, and development, their practicality is limited by an extremely long time-to-solution for realistic applications under investigation. This work describes a concerted effort, where machine learning (ML) is used to accelerate microarchitecture simulation. First, an ML-based instruction latency prediction framework that accounts for both static instruction properties and dynamic processor states is constructed. Then, a GPU-accelerated parallel simulator is implemented based on the proposed instruction latency predictor, and its simulation accuracy and throughput are validated and evaluated against a state-of-the-art simulator. Leveraging modern GPUs, the ML-based simulator outperforms traditional CPU-based simulators significantly.

Funder

U.S. Department of Energy

Publisher

Association for Computing Machinery (ACM)

Subject

Computer Networks and Communications,Hardware and Architecture,Safety, Risk, Reliability and Quality,Computer Science (miscellaneous)

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