System-level Logical Execution Time

Author:

Gemlau Kai-Björn1ORCID,KÖHLER Leonie1ORCID,Ernst Rolf1,Quinton Sophie2

Affiliation:

1. TU Braunschweig, Braunschweig, Germany

2. Inria Grenoble Rhône-Alpes, Montbonnot, France

Abstract

Logical Execution Time (LET) is a timed programming abstraction, which features predictable and composable timing. It has recently gained considerable attention in the automotive industry, where it was successfully applied to master the distribution of software applications on multi-core electronic control units. However, the LET abstraction in its conventional form is only valid within the scope of a single component. With the recent introduction of System-level Logical Execution Time (SL LET), the concept could be transferred to a system-wide scope. This article improves over a first paper on SL LET, by providing matured definitions and an extensive discussion of the concept. It also features a comprehensive evaluation exploring the impacts of SL LET with regard to design, verification, performance, and implementability. The evaluation goes far beyond the contexts in which LET was originally applied. Indeed, SL LET allows us to address many open challenges in the design and verification of complex embedded hardware/software systems addressing predictability, synchronization, composability, and extensibility. Furthermore, we investigate performance trade-offs, and we quantify implementation costs by providing an analysis of the additionally required buffers.

Funder

Deutsche Forschungsgemeinschaft

Bundesministerium für Bildung und Forschung

Publisher

Association for Computing Machinery (ACM)

Subject

Artificial Intelligence,Control and Optimization,Computer Networks and Communications,Hardware and Architecture,Human-Computer Interaction

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1. Logical Execution Time and Time-Division Multiple Access in Multicore Embedded Systems: A Case Study;Algorithms;2024-07-05

2. Optimizing Logical Execution Time Model for Both Determinism and Low Latency;2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS);2024-05-13

3. Optimizing End-to-End Latency of Sporadic Cause-Effect Chains Using Priority Inheritance;2023 IEEE Real-Time Systems Symposium (RTSS);2023-12-05

4. Supporting logical execution time in multi-core POSIX systems;Journal of Systems Architecture;2023-11

5. Automatic Deployment of Embedded Real-Time Software Systems to Hypervisor-Managed Platforms;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06

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