MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique-Reference-Cited by-同舟云学术

MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique

Published:2020-09-07 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2020 on Great Lakes Symposium on VLSI
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Author:

Zhuang Zhen¹,Liu Genggeng¹,Huang Xing¹,Jia Xiaotao²,Liu Wen-Hao³,Guo Wenzhong¹

Affiliation:

1. Fuzhou University, Fuzhou, China

2. Beihang University, Beijing, China

3. Block Implementation, ICD, Cadence Design Systems, Austin, TX, USA

Funder

National Natural Science Foundation of China

Fujian Natural Science Funds

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3386263.3406902

Reference14 articles.

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3. G. A. Constantinides "FPGAs in the cloud " in Proceedings of International Symposium on Field-Programmable Gate Arrays pp. 167--167 2017. G. A. Constantinides "FPGAs in the cloud " in Proceedings of International Symposium on Field-Programmable Gate Arrays pp. 167--167 2017.

4. The roles of FPGAs in reprogrammable systems

5. J. Babb R. Tessier and A. Agarwal "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators " in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines pp. 142--151 1993. J. Babb R. Tessier and A. Agarwal "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators " in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines pp. 142--151 1993.

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