On-chip FPGA Debug Instrumentation for Machine Learning Applications-Reference-Cited by-同舟云学术

On-chip FPGA Debug Instrumentation for Machine Learning Applications

Published:2019-02-20 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
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Author:

Holanda Noronha Daniel¹,Zhao Ruizhe²,Goeders Jeff³,Luk Wayne²,Wilton Steven J.E.¹

Affiliation:

1. University of British Columbia, Vancouver, BC, Canada

2. Imperial College London, London, United Kingdom

3. Brigham Young University, Provo, UT, USA

Funder

NSERC

Intel

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3289602.3293922

Reference15 articles.

1. Altera. 2015. Quartus Prime Pro Edition Handbook . Vol. 3. Chapter 9: Design Debugging Using the SignalTap II Logic Analyzer. Altera. 2015. Quartus Prime Pro Edition Handbook . Vol. 3. Chapter 9: Design Debugging Using the SignalTap II Logic Analyzer.

2. N. Calagar S.D. Brown and J.H. Anderson. 2014. Source-level Debugging for FPGA High-Level Synthesis. In Int'l Conf. on Field Programmable Logic and Applications . N. Calagar S.D. Brown and J.H. Anderson. 2014. Source-level Debugging for FPGA High-Level Synthesis. In Int'l Conf. on Field Programmable Logic and Applications .

3. F. Eslami and S. J. E. Wilton. 2015. An adaptive virtual overlay for fast trigger insertion for FPGA debug. In Int'l Conf. on Field Programmable Technology (FPT) . F. Eslami and S. J. E. Wilton. 2015. An adaptive virtual overlay for fast trigger insertion for FPGA debug. In Int'l Conf. on Field Programmable Technology (FPT) .

4. Effective FPGA debug for high-level synthesis generated circuits

5. Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits

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