Hardware support for balanced co-execution in heterogeneous processors

Author:

Perez Borja1ORCID,Bosque Jose Luis1ORCID

Affiliation:

1. Universidad de Cantabria, Spain, Santander

Funder

Spanish Science and Technology Commission

Publisher

ACM

Reference44 articles.

1. Alejandro Acosta, Robert Corujo, Vicente Blanco, and Francisco Almeida. 2010. Dynamic load balancing on heterogeneous multicore/multiGPU systems.. In HPCS, Waleed W. Smari and John P. McIntire (Eds.). IEEE, 467--476.

2. N. Agarwal D. Nellans E. Ebrahimi T. F. Wenisch J. Danskin and S. W. Keckler. 2016. Selective GPU caches to eliminate CPU-GPU HW cache coherence. In IEEE Int. Sym. on High Performance Computer Architecture (HPCA). 494--506.

3. AMD. 2023. AMD INSTINCT™ MI300A APU. Integrated CPU/GPU accelerated processing unit for high-performance computing generative AI and ML training. https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/data- sheets/amd-instinct-mi300a-data-sheet.pdf

4. StarPU: a unified platform for task scheduling on heterogeneous multicore architectures

5. R. Azimi, T. Fox, andS. Reda. 2017. Understanding the Role of GPGPU-Accelerated SoC-Based ARM Clusters. In 2017 IEEE Int. Conf. Cluster Computing. 333--343.

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