Using formal models to cross check an implementation
Author:
Affiliation:
1. Univ. Grenoble Alpes, Grenoble, France
2. Atos Worldgrid, Grenoble, France
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2933242.2933257
Reference30 articles.
1. IEEE Std 1012-2004. 2005. IEEE Std 1012 - 2004 IEEE Standard for Software Verification and Validation. (2005). IEEE Std 1012-2004. 2005. IEEE Std 1012 - 2004 IEEE Standard for Software Verification and Validation. (2005).
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3. A Methodology for Mapping SysML Activity Diagram to Time Petri Net for Requirement Validation of Embedded Real-Time Systems with Energy Constraints
4. Broad-spectrum studies of log file analysis
5. An Experiment on the Validation of a Specification by Heterogenous Formal Means: The Transit Node;Arnold A;DEPENDABLE COMPUTING AND FAULT TOLERANT SYSTEMS,1998
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