Multi-Layer Test and Diagnosis for Dependable NoCs
Author:
Affiliation:
1. Computer Architecture, University of Stuttgart, Pfaffenwaldring 47, D-70569 Stuttgart
2. Embedded Systems Engineering, University of Stuttgart, Pfaffenwaldring 5b, D-70569 Stuttgart
Funder
DFG
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/2786572.2788708
Reference35 articles.
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2. Enabling system-level modeling of variation-induced faults in networks-on-chips
3. Error control schemes for on-chip communication links: the energy-reliability tradeoff
4. Bushnell M. and Agrawal V.D. 2000. Essentials of electronic testing for digital memory and mixed-signal VLSI circuits. Chapters 7 & 8. Springer Science & Business Media. Bushnell M. and Agrawal V.D. 2000. Essentials of electronic testing for digital memory and mixed-signal VLSI circuits. Chapters 7 & 8. Springer Science & Business Media.
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